Method for producing solderable and functional surfaces on circuit carriers

ABSTRACT

The inventive method provides solderable areas in addition to bondable areas on circuit carriers, wherein solderability is not impaired by exposing the circuit carriers to the effects of temperature. The inventive method comprises the following steps: solderable surfaces are produced by deposition of a solderable metal layer ( 5 ), the solder areas are covered by a mask ( 6 ), functional surfaces ( 7, 8 ) are created in the functional areas and the covering mask ( 6 ) is finally removed.

DESCRIPTION

[0001] The invention relates to a process for the production of at leastone solderable surface in selected solder regions and of at least onefunctional surface in function regions differing from the solder regionson circuit carriers provided with copper surfaces as well as ofcorresponding circuit carriers.

[0002] Circuit carriers serve to receive active and passive components.In principle, a distinction is made between conventional printed circuitboards and chip carriers. Whereas the first ones are packed with passivecomponents such as capacitors and resistors for example and with casedsemiconductor components, the chip carriers serve for the assembly ofuncased semiconductor components. In parts, several uncased, andpossibly cased semiconductor components too, are integrated into asingle chip carrier. Such hybrid circuits are referred to as multichipmodules. For some time, uncased semiconductor components have beendirectly integrated, without prior assembly, into a circuit carriertogether with passive components. Such circuit carriers are so-calledCOB-(Chip-On-Board)-printed circuit boards.

[0003] Various processes for producing circuit carriers intended to bepacked with passive components and uncased semiconductor components havebeen known. First, the circuit pattern that is needed for this purposeand that is made from copper is formed by means of well-known processes.Then, layers of gold for example are deposited to allow the circuitcarriers to be packed. On one side, these layers serve to formsolderable surfaces which are necessary for the insertion of passivecomponents. On the other side, the gold surfaces are also suited forbonding cased and uncased semiconductor components.

[0004] U.S. Pat. No. 5,364,460 for example indicates that, among others,layers of gold are deposited by means of electroless plating ontoprinted circuit boards and cards for integrated circuits.

[0005] Coating copper structures on printed circuit board material isindicated in DE 43 11 266 A1. There, in one embodiment, parts of theprinted circuit board's surface are first plated with gold, palladium,indium, rhodium, nickel, tin; lead or alloys of these elements,preferably with palladium, in those regions that are not to be providedwith a solderable surface. Prior to this, the surface areas that are tobe provided with the solderable surface are provided with a coveringmask. Then, the mask is removed again. Thereupon, a solderable metalsurface of a Tin/lead alloy is formed by means of electroless plating.

[0006] DE 33 12 725 A1 describes a method of producing thin film stripconductors with through hole connections that can be bonded and solderedon electrically non-conductive carriers in which the areas that can bebonded and soldered are formed by galvanic deposition of a layer of goldor of nickel/gold, respectively.

[0007] Gold layers are also formed to produce electrical contacts thatmay be opened, such as plug contacts for plugging the packed circuitcarriers in contact plugs, and areas of contact for producing pressbuttons. DE-OS 1 690 338 mentions a method of producing multipleplug-type connections with gold surfaces in which, in the region of theplug-type connections and on the other circuit lines, a tin/lead alloyis first deposited by electroplating on a printed circuit board materialthat has been completely plated with a layer of copper whereupon nickeland gold are deposited in the region of the plugs onto the layer ofterne metal, the bare layer of copper being etched upon removal of theelectroplating lacquer. The reference indicates that the relatively softlayer located underneath the layer of nickel/gold is disturbing and thatit has been observed that the circuit lines happen to be etched throughat the transition zone between the gold contacts and the tin/lead alloy.

[0008] DE 197 45 602 C1 further indicates that layers of gold areutilized for producing surfaces that are capable of being soldered,glued or bonded. The methods described in this reference permit toproduce circuit carriers of the finest structure with surface-mountedsemiconductor circuits in which the circuits are connected to matingconnecting pads on the circuit carrier by way of Ball-wedge-Bonds.

[0009] Layers of gold that have been produced by means of electroplatingare not applied directly onto the copper surfaces. According to U.S.Pat. No. 5,364,460 for example, a layer containing nickel is depositedfirst and then the film of gold is deposited onto the layer containingnickel. The nickel containing layer is preferably formed by a layer ofNi/B or Ni/P which is deposited by means of electroless plating. U.S.Pat. No. 5,470,381 also teaches to first deposit a layer containingnickel and then a layer of gold.

[0010] DE 197 45 602 C1, U.S. Pat. No. 5,202,151, U.S. Pat. No.5,318,621, U.S. Pat. 5,364,460 and U.S. Pat. No. 5,470,381 describemethods of electroless gold plating.

[0011] Instead of the layer containing nickel, layers of another metal,of cobalt or palladium for example, can be deposited onto the coppersurfaces prior to forming the layer of gold. In this respect, U.S. Pat.No. 5,202,151 proposes among other suggestions to apply a layer ofcobalt to the copper surfaces and to deposit the layer of goldsubsequently. Instead of electroplating a layer of nickel or cobalt, alayer of nickel or cobalt can also be applied by means of a vapordeposition process or by sputtering and then be electrolessly goldplated. DE 197 45 01 C1 moreover indicates a method of producing goldlayers on a work piece that is provided with a palladium surface.

[0012] Instead of using a layer of gold, layers of palladium can also beutilized. DE 42 01 129 A1 describes a method of producing a wiring boardin which a film of palladium is formed on the copper parts of the boardby means of electroless plating, the palladium surfaces being producedon double-faced wiring boards in order to bond components of thesurface-mounted technology-type by soldering them. Furthermore, U.S.Pat. No. 4,424,241 indicates a process of electrolessly platingpalladium in which the layers of palladium formed serve for patterndelineation in electric circuits such as integrated circuits.

[0013] To produce layers of gold on the entire surface of the circuitcarrier proved to be too expensive. In most cases, smaller bondableareas only are needed on the surfaces of the circuit carriers whileother surface areas only need to be suited for receiving components thatare mounted by soldering. It has moreover been noticed that layers ofgold with underlying layers of nickel for soldering so-calledBall-Grid-Arrays (BGA) lead to brittle fractures when the packed circuitcarrier is subject to mechanical and/or thermal stress.

[0014] For this reason, a process has been developed in which thoseareas onto which components are intended to be soldered are firstcovered with an appropriate mask e.g. a photoresist that can bestructured, whereupon a layer combination of nickel and gold isdeposited on the still bare areas. Then, the mask is cleared off thesurface of the circuit carrier. Subsequently, an organic protectivecoating is formed by means of an aqueous acid solution of alkylimidazole or of alkyl benzimidazole compounds. This protective coatingprevents the copper surfaces from oxidizing and preserves solderabilityof the copper surfaces.

[0015] First, with this process, the combination layer of nickel andgold is only formed in those areas in which components are bonded or inwhich electric contact areas are needed. Second, this process eliminatesthe problem associated with soldering by means of the BGA technique.

[0016] It has been observed in carrying out this process though, thatthe appearance of the gold surfaces unfavorably changes in that thelayers change to a reddish colour. Additionally, the layer of nickelunderneath the layer of gold is damaged by the processing chemicals. Asa result, the electrical contact resistance is increased so that thepossibility of using the combination layer of nickel and gold to formelectrical contact areas is limited.

[0017] Soldering moreover proved to cause problems: it is virtuallyimpossible to solder repeatedly at connection places for the components.Each soldering procedure performed after the first soldering increasesthe waste ratio. The only possibility of having soldering proceduresperformed repeatedly at connection places is to use a complicatedremelting method employing inert gas (nitrogen for example) andexpensive remelting devices. Sometimes wetting problems also occur onthe copper surfaces provided with the organic protective coating.

[0018] The basic problem of the present invention therefor is avoidingthe shortcomings of the known methods and more specifically finding aprocess by means of which components may be mounted on the surface of acircuit carrier both by bonding and by soldering as well. The inventionmoreover aims at producing soldered joints that are secure and do notcause any problem and at making it possible to repeat solderingprocedures at individual connection places for components without anyproblem. The process furthermore is to be inexpensive and itsrealization simple. The process is to allow to form finest circuitstructures, more specifically circuit lines and connection places forelectronic components, wherein the structures with steep sides are to bereproducible.

[0019] The problem is solved by the process of claim 1 and the circuitcarrier of claim 14. Preferred embodiments of the invention are recitedin the subclaims.

[0020] The process according to the invention serves to create at leastone solderable surface in selected solder regions and at least onefunctional surface in function regions differing from the solder regionson surfaces of copper structures on circuit carriers. The preferablycreated functional surface is a bondable surface. In principle, thefunctional surfaces can also be suited for producing electrical contactsthat can be opened.

[0021] The process involves the following steps:

[0022] (a) first, a dielectric substrate provided with copper structuresis provided;

[0023] (b) then, the solderable surfaces are created by depositing asolderable layer of metal;

[0024] (c) then, a covering mask is formed that covers the solderregions and leaves the function regions uncovered;

[0025] (d) subsequently, the functional surfaces are created in thefunction regions and

[0026] (e) the covering mask is eventually cleared off.

[0027] The process according to the invention constitutes an inexpensiveprocess since a functional surface is only formed in those regions onthe surface of the circuit carriers in which bonded connections with thecomponents are to be formed, whereas in the regions in which solderedconnections are to be formed, an inexpensive solderable layer of metalis deposited. Furthermore, in using the BGA-technique, brittle fractureshave not been observed.

[0028] A particular advantage thereof is the increased soldering safetyas compared to the method using organic protective coatings for thecopper surfaces. Most of all, the waste ratio with respect tosolderability both in producing and in packing the circuit carriers aswell is less than with the known methods. Repeated remelting orsoldering of individual connection places for the components is possiblewithout any problem. The wetting with the solder on the solderablesurfaces formed according to the invention proved for example to stilllie within the required tolerance even after remelting has taken placefor the third time. Furthermore, the circuit carriers produced accordingto the invention proved to have very good storing properties, which arenot detrimental to the solderability in the solder regions.

[0029] Additionally, the process according to the invention is notdetrimental to the appearance of layers of gold serving as functionallayers. The electric contact resistance of these layers is suited forforming electric contact areas that can be opened.

[0030] Another advantage over the method described in DE-OS 1 690 338 isthat the circuit lines and connection places for electronic componentsthat can be formed by means of the process according to the inventionare very small, with a grid of 100 μm and less for example. The sides ofthe circuit lines and the connection places are very uniform, i.e., theyhave very steep sides and a constant width. More specifically, noetching flaws such as undercuts, constrictions in the circuit lines oreven disruption of the circuit lines, can be found.

[0031] To produce a solderable surface, preferably at least one metal,selected from the group comprising of tin, silver, bismuth, palladiumand alloys thereof, is deposited. These metals can be deposited by meansof electroless plating, i.e., in a chemically reductive or cementativemanner so that even electrically isolated structures located on thesurface of the circuit carriers can be plated with the solderable layerwithout any problem.

[0032] In the event the individual copper structures are stillelectrically connected in the manufacturing process, an electrolyticmetal deposition method may also be employed. This is for example thecase when the individual structures are first still connected to theso-called galvanic border, which is a greater copper conducting layer onthe border of the circuit carrier material. In the process of producingthe circuit carrier, this border is removed so that the circuitstructures are electrically isolated from each other.

[0033] In that the circuit structures are already formed when thesolderable layer and the functional layer are being produced, the sidesof the structures, more specifically connection places for electroniccomponents, may be plated with the solder layer and with the functionlayer. This results in an additional protection from corrosion and otherdetrimental influences. If the circuit structures were, e.g. formed byetching only after the solderable and functional layers have beenapplied, which is for example the case according to DE-OS 1 690 338, theunprotected sides of the circuit structures would possibly be attackedin the etching procedure so that the circuit structures created wouldnot have uniform sides.

[0034] This problem does not exist with the process according to theinvention. Therefor, very uniform circuit structures with even thesmallest dimensions can be formed.

[0035] For tin deposition, the copper surfaces on the circuit carrierare first preferably cleaned, in particular with a cleaning solution(which is acid and contains surface-active agents). Then, the remaindersof the cleaning solution are rinsed off the surfaces. Then, the coppersurfaces are preferably etched slightly in order to make certain ofsufficient adhesion of the metal layers applied subsequently. For thispurpose, a commercial cleaning etch may be used, like for example anaqueous, sulfuric acid solution of hydrogen peroxide or of a caroatesalt or an aqueous solution of sodium peroxodisulfate. After cleaninghas been carried out by means of etching, the copper surfaces are rinsedagain and then preferably treated by preliminary immersion into asolution of an acid, more specifically of sulfuric acid. Moreover, thecopper surfaces can be catalysed with a solution that contains noblemetal ions prior to treating them by preliminary immersion into the acidsolution, which results in greater ease of tin deposition.

[0036] A conventional treating solution can be utilized for tindeposition. A cementative tin deposition bath is preferably used. Inaddition to at least one tin(II) compound, such baths contain acid andusually thiourea or a derivative of thiourea. These baths contain forexample 15 g tin(II) fluoroborate, 100 ml fluoroboric acid, 100 gthiourea and 2 mg sodium lauryl sulfate in 1 l of an aqueous solution or5 g tin(II) chloride, 55 g N-methyl thiourea, 20 g sulfuric acid,concentrated, 500 ml isopropanol and 500 ml water or 20 g tin(II)chloride, 25 ml hydrochloric acid (37% by weight), 50 ml sulfuric acid(50% by weight), 16 g sodium hypophosphite, 200 g thiourea and 0.5 gphenolsulphonic acid in 1 l of an aqueous solution. The treatmenttemperature amounts to 40-90° C. Treatment time ranges from 30 sec to 60min. Further examples of such tinning baths are indicated in DE 30 11697 A1, WO 99/55935 A1 and U.S. Pat. No. 4,816,070 for example. Theformulations indicated in these documents are included in the processaccording to the invention as formulations that may be utilized.

[0037] Stated in general terms, to electrolessly deposit silver, thesurfaces of the circuit carriers are first cleaned, then rinsed,subsequently treated with a bright etching solution (for example aH₂SO₄/H₂O₂ solution) and then rinsed again. Thereupon, the surfaces arepreferably pretreated by preliminary immersion thereof in a solutioncontaining sulfuric acid.

[0038] Then, the layer of silver is applied. For silver deposition asolution may be used that for example consists of a bath which has thefollowing composition: 200 g sodium thiosulfate, 20 g sodium sulfite,0.1 g disodium EDTA, 3 g silver as a silver-thiosulfate/sulfite complex,5 g glycine in 1 l of an aqueous solution. The pH can be adjusted toapproximately 7.5 for example and the treatment temperature topreferably 50-95° C. Treatment time amounts to 15 min. for example.Further examples are indicated in U.S. Pat. No. 5,318,621 among others.The formulations indicated in these documents are also included in theprocess according to the invention as formulations that may be utilized.

[0039] After the silver layer has been formed, the surfaces arepreferably treated with an inorganic saline solution and then rinsed.

[0040] For the electroless deposition of palladium, a solution may forexample be used that comprises 0.05 mol palladium acetate, 0.1 molethylene diamine, 0.2 mol sodium formiate and 0.15 mol succinic acid in1 l of an aqueous solution. The pH of this bath is preferably adjustedto 5.5 and the temperature to about 70° C. Further possible formulationscomprise for example: 0.01 mol palladium chloride, 0.08 mol ethylenediamine, 20 mg thiodiglycolic acid and 0.06 mol sodium hypophosphite in1 l of an aqueous solution (pH 8, 60° C.). Further indications andexamples as well as appropriate conditions for pretreating the surfacesto be coated are to be found for example in DE 197 45 602 C1, DE 42 01129 A1 and U.S. Pat. No. 4,424,241. The formulations indicated in thesedocuments are included in the process according to the invention asformulations that may be utilized.

[0041] Once the solderable surfaces have been produced by depositing thesolderable layer of metal, a covering mask is formed according to step(c) of the process, the solderable regions being covered by the mask.The function regions hereby remain free so that the functional surfacesmay be produced in the function regions at a later stage (step (d) ofthe process).

[0042] To produce the covering mask, a structured photomask ispreferably formed on the surface of the circuit carrier. The mask iscreated by using a photoresist and by carrying out the followingsequential steps:

[0043] (c1) application of a layer of photoresist,

[0044] (c2) exposure of the layer of photoresist with a model of themask in such a manner that the function regions can be led bare in asubsequent development stage and

[0045] (c3) development of the exposed layer of photoresist.

[0046] In an alternative variant of the embodiment, the mask whichcovers the solder regions and does not cover the function regions canalso be formed by means of a screen printing process.

[0047] If tin, bismuth or an alloy of these metals are used to producethe solderable surface, the solderable layer of metal in the functionregions is removed again, preferably by means of an acid etch solutionprior to carrying out step (d) of the process. To remove these metals,an etch solution containing nitric acid and inhibitors (preferablyimidazole derivatives) may be utilized. Palladium and silver as well astheir alloys, when they form a solderable layer of metal, do not have tobe removed. In this event, the function layer can be deposited on thelayer of palladium, silver or of an alloy of these metals.

[0048] The functional surfaces are preferably formed by at least onemetal selected from the group comprising of gold, palladium, silver andtheir alloys. The surfaces are more specifically formed by chemicallyreductive or cementative deposition. The deposition of particularpreference is the deposition of a combined layer consisting of a layerof nickel and of a layer of gold applied on said layer of nickel. Thecircuit carrier according to the invention is preferably provided withat least one solderable surface of at least one metal selected from thegroup comprising tin, silver, palladium and their alloys and with atleast one functional surface of gold, the surface of gold being formedby a combination layer consisting in a layer of nickel onto which goldis plated.

[0049] Prior to forming a layer of gold, a layer of nickel/phosphorus ispreferably deposited by chemical reduction. As an alternative, a layerof nickel/bor or a layer of pure nickel can also be deposited. To formthese layers, the circuit carriers may first be contacted with asolution containing a surface-active agent in order to completely wetthe surfaces with the fluid. Thereupon, rinsing is performed. Then, thebare copper surfaces are etched by means of a commercial cleaning etch.Excess etch is then removed in another rinsing step. Then, the surfacescan be treated with a solution for preliminary immersion that containssulfuric acid and then treated in an activating solution comprisingpalladium sulfate with a content of 80-120 mg/l of palladium andsulfuric acid with a content of approximately 50 ml/l. After thesurfaces have been rinsed anew, a layer of nickel, nickel/phosphorus ornickel/bor is deposited.

[0050] Chemical nickel baths are actually known. Customarily, thesebaths are operated at a temperature ranging from 85 to 90° C.Solderability of tin layers proved to have a particularly advantageousbehaviour when temperature stress in depositing nickel is low. For thisreason, the preferably used nickel baths are operated at a temperaturebelow 85° C., more specifically below 80° C., the nickel bath ofparticular preference being operated at a temperature below 75° C. Ithas been found that particularly favourable conditions are reached whena temperature of from 70 to 75° C. is adjusted for the electrolessdeposition of nickel.

[0051] For the electroless deposition of gold, baths having thefollowing formulation can be used: 0.015 mol sodiumtetrachloroaurate-(III), 0.1 mol sodium thiosulfate, 0.04 mol thiourea,0.3 mol sodium sulfite and 0.1 mol sodium tetraborate in 1 l of anaqueous solution (pH 8.0, 90° C.) or 3 g sodium gold(I) sulfite, 70 gsodium sulfite, 110 g sodium ethylene diamine tetra(methylenephosphonate) and 10 g hydrazine hydrate in 1 l of an aqueous solution(pH 7, 60° C.). Further examples are indicated in U.S. Pat. No.5,202,151, U.S. Pat. No. 5,364,460, U.S. Pat. No. 5,318,621 and U.S.Pat. No. 5,470,381 for example. The formulations indicated in thesedocuments are included in the process according to the invention asformulations that may be utilized.

[0052] If the layer of gold is directly deposited on a layer ofpalladium that may be used as a solderable layer of metal with noadditional layer of nickel, the following formulation may be used forexample: 3 g sodium gold(I) cyanide, 20 g sodium formiate, 20 gβ-alanine diacetic acid in 1 l of an aqueous solution (pH 3.5, 89° C.).Further examples of this application are indicated among others in DE197 45 602 C1. The formulations indicated in these documents areincluded in the process according to the invention as formulations thatmay be utilized.

[0053] If the layer of gold is deposited on a layer of palladium that isutilized as a solderable layer of metal with an additional layer ofnickel, the sequence observed for the process is as follows:

[0054] First, the circuit carriers that are provided with the surfacesof palladium are contacted with a solution containing surface-activeagents in order to make sure that the entire surface be wetted withfluid. Then, excess surface-active solution is rinsed off again and alayer of nickel is thereupon deposited in a well-known manner. The layerof gold is formed upon rinsing.

[0055] To deposit a combination layer of nickel/gold on a layer ofsilver, the circuit carriers provided with the layer of silver arepreferably first treated with a wetting solution, whereupon they arerinsed, subsequently treated in a solution for preliminary immersioncontaining inorganic salts and finally treated with a silver activationsolution. After renewed rinsing, the layer of nickel can be applied andupon another rinsing step, the layer of gold.

[0056] To deposit layers of palladium and silver, reference is made tothe above mentioned examples for producing solderable surfaces.

[0057] Prior to performing step (b) of the process, the circuit carriersprovided with the copper surfaces are preferably provided with a solderresist mask.

[0058] The process as it has been presented can be carried out in aconventional way in plating tanks, the circuit carriers being fastenedonto racks and being dipped one after the other together with the racksfrom which they are vertically hanging into the discrete treating baths.An advantageous treatment consists in conveying the circuit carriersthrough a conventional continuous plant in which the circuit carriersare conveyed through the plant in horizontal direction of transportationand horizontal or vertical operational position, thereby beingsuccessively brought into contact with the discrete treating solutions.For this purpose, these solutions are delivered to the surfaces of thecircuit carriers by way of nozzles. In these plants the circuit carriersmay also be conveyed through a banked-up bed of fluid though, with nonozzles provided for delivering the treating solution.

[0059] The following examples as well as FIG. 1 that shows an exemplaryembodiment of the invention serve to explain more fully the presentinvention. FIG. 1 shows the steps of the process according to theinvention in schematic form:

[0060] According to step A of the process, the initial condition isshown, copper structures 2 and 4 being represented on a substrate 1 ofthe circuit carrier. The connection places formed from the copperstructures 2 serve to mount components which are attached by soldering.The connection places formed from the copper structures 4 serve to mountcomponents with are attached by bonding. In principle, the copperstructures 4 can also serve to produce contact areas. Regions providedwith a solder resist mask 3 can be seen between the copper structures 2and 4.

[0061] In the present example, a layer of tin 5 is first deposited ontoall the copper surfaces of the structures 2 and 4 (step B of theprocedure).

[0062] Then, a covering mask 6 is applied over those regions on thecircuit carrier that are to be provided with a solderable surface (stepC of the procedure). The covering mask 6 applied is a layer ofphotoresist that can be structured, said layer being accomplished bylamination of a commercial dry film resist, subsequent exposure of thelayer of resist with the desired pattern for the bonding places anddevelopment of the exposed layer of resist.

[0063] In accordance with step D of the process, the layer of tin 5 issubsequently completely removed from the copper structures 4 by means ofa tin stripper.

[0064] Then, a nickel/phosphorus layer 7 is deposited onto the surfacesof the copper structures 4 that have been laid bare and a layer of gold8 is deposited onto the layer of nickel/phosphorus 7 (step E of theprocess).

[0065] To conclude, the covering mask 6 is cleared off again (step F ofthe process).

EXAMPLE 1

[0066] A completely structured printed circuit board that has beenprovided with strip conductors, solder pads, bond pads, circuitstructures and metallized bores is coated with a solderable layer of tinaccording to the following Process Sequence I: Process Sequence I:Treatment time Temperature Process stage [min] [° C.] cleaning 3-6 30-40rinsing 2-3 ambient temperature etching 2-3 20-30 rinsing 2-3 ambienttemperature preliminary immersion 1-3 25-35 tin deposition  8-15 58-68

[0067] The cleaning solution used was an acid solution comprisingsurface-active agents, the etching solution was a sulfuric acid solutioncomprising sodium peroxodisulfate and the solution for preliminaryimmersion was a solution comprising sulfuric acid. The solution for tindeposition had the following formulation:

[0068] 10 g/l tin²⁺ as tin salt

[0069] 80 g/l thiourea

[0070] 80 ml/l methane sulfonic acid

[0071] A film of tin, of from 0.6 to 1.0 μm thick, was deposited underthe conditions applied.

[0072] Then, the board was provided with a covering mask by laminating adry film resist (W140 from DuPont de Nemours, Germany) on the surfacesof the printed circuit boards in accordance with the directions for use,exposing the layer of resist with the desired pattern and subsequentlydeveloping the exposed layer of resist. After the structuring processhad been carried out, some of the regions were covered by the resist(solder regions), others were lying bare (function regions).

[0073] The layers of tin lying bare in the function regions and theintermetallic tin/copper phases on the copper structures were thenremoved by means of a tin stripper containing nitric acid.

[0074] After the circuit board had been rinsed in a subsequent step, alayer of nickel/phosphorus was first electrolessly deposited onto thebare copper surfaces and then a layer of gold. For this purpose, thefollowing Process Sequence II was employed: Process Sequence II:Treatment time Temperature Process stage [min] [° C.] wetting 2-3 30-40rinsing 2-3 room temperature etching 2-3 20-30 rinsing 2-3 roomtemperature preliminary immersion 3-5 room temperature activation 1-3room temperature rinsing 2-3 room temperature nickel deposition 20-3070-80 rinsing 2-3 room temperature gold deposition  8-12 70-80

[0075] Again, the cleaning solution used was an acid solution comprisingsurface-active agents, the etching solution was a sulfuric acid solutioncomprising sodium peroxodisulfate and the solution for preliminaryimmersion was a solution comprising sulfuric acid. The solution for theelectroless deposition of nickel had the following formulation:

[0076] 24-34 g/l NiSO₄.7H₂O

[0077] 30-40 g/l NaH₂PO₂.H₂O

[0078] 15-25 g/l lactic acid stabilizers.

[0079] A layer of nickel/phosphorus, of from 3 to 6 μm thick, wasdeposited.

[0080] The solution for electrolessly depositing gold had the followingformulation:

[0081] 2 g/l Au⁺ of a complex gold salt

[0082] 40 g/l ethylene diamine tetraacetic acid

[0083] A layer of gold, of from 0.05 to 0.10 μm, was deposited.

[0084] Upon deposition of gold, the structured layer of photoresist wascleared off the surface of the printed circuit board by means of aconventional method, the board was rinsed and dried intensively.Accordingly, the finished printed circuit board showed regions that werecoated with tin for soldering and with a combination layer of nickel andgold for carrying out bonding processes as well as for function layerserving other purposes, such as electric contact areas for example.

[0085] To determine solderability of the copper structures coated withthe chemical layer of tin, tests were performed for wetting the surfaceswith liquid solder by means of the so-called Solder-Spread-Test. Forthis purpose, the wetting angle was indirectly determined upon wettingby measuring the size of a melted solder globule which permitted tocalculate the wetting angle. Particularly good wetting was ascertainedwhen the determined wetting angle was small. The average wetting angleshould lie below 10°, standard deviation should not be in excess of 1°.

[0086] The following conditions were compared:

[0087] 1) A chemical layer of tin was applied onto a copper surface andthe wetting test was performed on the layer of tin.

[0088] 2) The wetting test was performed on the chemically formed layerof tin upon removal of the dry resist (in accordance with step C of theprocess according to FIG. 1).

[0089] 3) The wetting test was performed upon application of thecombination layer of nickel and gold and upon removal of the dry resistby means of a solution comprising methanol amine at 50° C. andsubsequent first rinsing in a solution that also contained methanolamine and subsequent second rinsing in de-ionized water (in accordancewith step F of the process according to FIG. 1.)

[0090] Two different dry film resists were used as covering masks(resist 1: W140 from DuPont de Nemours, resist 2: HW440 from Hitachi).

[0091] Table A below indicates the determined wetting angles yielded bythe wetting test: TABLE A Test Condition 1 Test Condition 2 TestCondition 3 (chem. Sn) (after step C) (after step F) Resist 1 4.9° ±0.6° 5.9° ± 0.8° 5.7° ± 0.7° Resist 2 6.0° ± 0.7° 4.7° ± 0.9° 6.2° ±0.8°

[0092] Then, the tests were repeated, this time however, a bath ofnickel was used in which the coating temperature was adjusted to rangefrom 85 to 90° C. The determined wetting angles are indicated in TableB: TABLE B Test Condition 1 Test Condition 2 Test Condition 3 (chem. Sn)(after step C) (after step F) Resist 1 3.9° ± 1.0° 9.9° ± 0.9° 14.5° ±1.7° Resist 2 4.8° ± 0.5° 11.3° ± 0.9°  12.2° ± 1.1°

[0093] The results yielded by the wetting tests clearly show that verygood soldering results are obtained when the temperature of the nickelbath is low.

EXAMPLE 2

[0094] A printed circuit board structured according to the processdescribed in Example 1,but additionally provided with a solder resistmask that partially covered the copper structures, was plated with athin layer of palladium according to Process Sequence III: ProcessSequence III: Treatment time temperature Process stage [min] [° C.]cleaning 2-6 30-40 rinsing 2-3 room temperature etching 2-3 20-30rinsing 2-3 room temperature preliminary immersion 3-5 room temperatureactivation 3-5 30 rinsing 1-2 room temperature deposition of Pd 4-855-65

[0095] Again, the cleaning solution used was an acid solution comprisingsurface-active agents, the etching solution was a sulfuric acid solutioncomprising sodium peroxodisulfate and the solution for preliminaryimmersion was a solution comprising sulfuric acid The solution for theelectroless deposition of palladium had the following formulation:

[0096] 0.7-1.2 g/l Pd²⁺ as palladium sulfate

[0097] 10 g/l ethylene diamine

[0098] 0.2 mol/l sodium formiate.

[0099] A film of palladium, of from 0.1 to 0.25 μm, was deposited.

[0100] Then, a covering mask was applied onto the surface of the printedcircuit board and structured, the conditions and materials used beingidentical with those used in Example 1.

[0101] Then, a combination layer of nickel and gold was directly appliedonto the layer of palladium according to Process Sequence IV. ProcessSequence IV: Treatment time temperature Process stage [min] [° C.]wetting 2-3 30-40 rinsing 2-3 room temperature deposition of nickel20-30 70-80 rinsing 2-3 room temperature deposition of gold  8-12 70-80

[0102] A solution containing surface-active agents was used to wet thesurfaces of the circuit carriers. The formulation for the solutions forthe electroless deposition of nickel or gold respectively was the samethan for the solutions for depositing nickel and gold respectively thatwere indicated in Example 1. A layer of nickel, of from 3 to 6 μm thick,and a layer of gold, of from 0.05 to 0.10 μm thick, were deposited.

[0103] The subsequent treatment of the printed circuit board aiming atremoving the covering mask was identical to that according to Example 1.

[0104] Besides solder regions with palladium surfaces, the board hadregions with gold surfaces for high-grade functions.

EXAMPLE 3

[0105] A printed circuit board structured and coated with a solderresist mask according to Example 2 was electrolessly silver plated inaccordance with Process Sequence V: Process Sequence V: Treatment timetemperature Process stage [min] [° C.] cleaning 3-6 30-40 rinsing 2-3room temperature bright etching 2-3 20-30 rinsing 2-3 room temperaturepreliminary immersion 1 room temperature deposition of silver 1-2 35-45subsequent immersion 1 room temperature rinsing 1-2 room temperature

[0106] To clean the surfaces of the circuit carriers, an acidic solutioncomprising surface-active agents was again used, the bright etchsolution used comprised H₂O₂/H₂SO₄, the solution for preliminaryimmersion utilized was a solution comprising inorganic salts and thesolution for subsequent immersion was a solution containing inorganicsalts as well.

[0107] A layer of silver, of from 0.10 to 0.20 μm thick, was deposited.

[0108] Then, a covering mask was applied onto the surface of the printedcircuit board and was structured, the conditions and the materials usedbeing identical to those used in Example 1. As a result, the silversurfaces were partially left open. These surfaces were subsequentlyprepared for nickel/gold deposition by means of an activation processand then plated with a combination layer of nickel and gold. The silverlayer was not removed. The Process Sequence VI used therefor isindicated below: Process Sequence VI: Treatment time Temperature Processstage [min] [° C.] wetting 2-3 30-40 rinsing 2-3 room temperaturepreliminary immersion 3-5 room temperature activation of silver 1-3 roomtemperature rinsing 2-3 room temperature deposition of nickel 20-3070-80 rinsing 2-3 room temperature deposition of gold  8-12 70-80

[0109] The wetting solution and the solution for preliminary immersionused had the same composition as those used in the Examples 1 and 2. Thesolution used to activate with silver contained Pd(NO₃)₂. The solutionsfor the electroless deposition of nickel and gold respectively had thesame compositions as the solutions for depositing nickel and goldrespectively used in Example 1. A layer of nickel, of from 3 to 6 μmthick, and a layer of gold, of from 0.05 to 0.10 μm thick, weredeposited.

[0110] The subsequent treatment of the printed circuit board aiming atremoving the covering mask was identical to the treatment in Example 1.

[0111] Besides pads and bores clad with silver destined to soldering,regions serving for high-grade functions were plated with thecombination layer of nickel and gold.

[0112] Comparative test V1:

[0113] A printed circuit board with strip conductors, solder pads, bondpads, circuit structures and metallized bores was provided with a solderresist mask and treated according to the following Process Sequence VII:Process Sequence VII: Application of a layer of dry film resist Exposurewith the desired pattern Development of the exposed resist Deposition ofnickel Deposition of gold Removal of the resist Application of anorganic protective coating

[0114] The conditions and materials used for application, exposure,development and removal of the dry film resist upon deposition of thecombination layer of nickel and gold were identical to the conditionsprevailing and the materials used in Example 1. The processingconditions and the compositions of the baths for depositing the layer ofnickel and the gold layer were also identical to the conditionsprevailing and the compositions of the baths used in Example 1.

[0115] To apply the organic protective coating, a solution comprising

[0116] 10 g/l 2-n-heptyl benzimidazole

[0117] 32 g/l formic acid in water

[0118] was applied at 40° C. for 2 min. For this purpose, the barecopper surfaces were first pretreated with an etch solution containingKHSO₅ and H₂SO₄.

[0119] The aging stability of the solderable surfaces was determined onthe thus produced printed circuit boards (test articles labelled with“OSP”). The results obtained were compared with the results that hadbeen obtained on tin surfaces produced according to the process used in

[0120] Example 1 (test articles labelled with “chem. Sn”).

[0121] To evaluate the aging stability the test articles were eachsubjected to different conditions of temperature:

[0122] 1) Tests with articles without temperature treatment;

[0123] 2) Tests with articles that were submitted to a reflow procedureonce;

[0124] 3) Tests with articles that were submitted to a reflow procedurethree times;

[0125] 4) Tests with articles that were tempered in air at 155° C. for 4hours.

[0126] Reflow was carried out under the following conditions: a certainquantity of the soldering paste RP 10 of Multicore was pressed upon thesurfaces to be tested at a thickness of 120 μm and then heated in areflow oven to a temperature exceeding the melting point. The solder ofthe paste liquefied in the process and spread over the wettablesurfaces.

[0127] The wetting time t_(B) [sec], the wetting force F₂[mN/mm] after 2sec and the wetting force F₆ [mN/mm] after 6 sec were measured for eachtest article by means of a soldering scales (Menisto ST-50 byMetronelec, FR). Solderability of the surfaces tested was the higher,the lower the wetting time and the higher the wetting force.

[0128] The results are summarized in Table C: TABLE C Test Article AgingTest t_(B) [sec] F₂ [mN/mm] F₆ [mN/mm] chem. Sn Test condition 1 0.350.181 0.179 OSP Test condition 1 0.53 0.164 0.170 chem. Sn Testcondition 2 0.54 0.185 0.184 OSP Test condition 2 0.78 0.089 0.086 chem.Sn Test condition 3 0.7  0.158 0.186 OSP Test condition 3 0.96 0.0850.088 chem. Sn Test condition 4 1.13 0.094 0.139 OSP Test condition 4 nowetting −0.184 −0.186

[0129] The results indicated above clearly show that temperaturetreatment is not prejudicial to the solderability of the surfacesproduced by means of the process according to the invention. The valuesobtained further reveal that the wetting time is the longer the moretemperature treatment is important. The wetting force is substantiallyindependent of the temperature stress. Therefrom it may be inferred thatno adverse consequences due to aging of the solderable surfaces producedaccording to the process of the invention ensue.

[0130] By contrast, the solderability of the copper surfaces plated withthe organic protective coating suffers considerably from the temperaturetreatmnent. Test articles aged under test condition 4 cannot be solderedany more at all.

1. Process for the production of at least one solderable surface inselected solder regions and of at least one functional surface infunction regions differing from the soldering regions on surfaces ofcopper structures on circuit carriers with the following sequentialprocess stages: (a) a dielectric substrate provided with copperstructures is prepared; (b) the solderable surfaces are created bydepositing a solderable layer of metal; (c) a covering mask is formedthat covers the solder regions and leaves the function regionsuncovered; (d) the functional surfaces are created in the functionregions and (e) the covering mask is cleared off.
 2. Process accordingto claim 1, wherein the at least one solderable surface is made from atleast one metal selected from the group comprising tin, silver, bismuth,palladium and their alloys.
 3. Process according to one of the precedingclaims, wherein the at least one solderable surface is formed bydepositing at least one solderable layer of metal by means of chemicalreduction or cementation.
 4. Process according to claim 3, wherein theat least one solderable layer of metal is removed again prior tocarrying out stage (d) of the process in the function regions. 5.Process according to claim 4, wherein the at least one solderable layerof metal is removed by means of an acid etch solution.
 6. Processaccording to one of the preceding claims, wherein the at least onebondable surface is produced to serve as a functional surface. 7.Process according to one of the preceding claims, wherein the at leastone functional surface is made of at least one metal, selected from thegroup comprising gold, palladium, silver and their alloys.
 8. Processaccording to claim 7, wherein, for the purpose of producing the at leastone functional surface, a basic layer is first applied, said layer beingmade from a metal selected from the group comprising nickel, cobalt andtheir alloys.
 9. Process according to one of the preceding claims,wherein, for the purpose of producing the at least one functionalsurface, a layer comprising nickel is deposited first and a layer ofgold is applied there onto.
 10. Process according to one of thepreceding claims, wherein the at least one functional surface is formedby the deposition of at least one functional layer by means of chemicalreduction or cementation.
 11. Process according to one of the precedingclaims, wherein the covering mask is formed by performing the followingsteps: (c1) application of a layer of photoresist, (c2) exposure of thelayer of photoresist with a model of the mask in such a manner that thefunction regions can be led bare in a subsequent development stage and(c3) development of the exposed layer of photoresist.
 12. Processaccording to one of the preceding claims, wherein the covering mask isformed by means of a screen printing process.
 13. Process according toone of the preceding claims, wherein the circuit carriers provided withthe copper surfaces are provided with a solder resist mask prior tocarrying out step (b) of the procedure, the solder regions and thefunction regions remaining bare.
 14. Circuit carrier with at least onesolderable surface in selected solder regions and with at least onefunctional surface suited for bonding in function regions that aredifferent from the solder regions, the at least one solderable surfaceconsisting of at least one metal selected from the group comprising tin,silver, bismuth, palladium and their alloys and that the at least onefunctional surface consists of gold.
 15. Circuit carrier according toclaim 14, wherein a layer containing nickel and thereupon a layer ofgold are arranged in the function regions.